公开(公告)号：US09306844B2

公开(公告)日：2016-04-05

申请号：US13673505

申请日：2012-11-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Riccardo Locatelli ,  Esa Petri ,  Antonio-Marcello Coppolla ,  Luca Fanucci ,  Sergio Saponara ,  Tony Bacchillone

IPC: H04L12/28 ,  H04L12/741 ,  H04L12/775 ,  H04L12/931 ,  H04L12/933 ,  H04L12/721 ,  H04L12/773

CPC classification number: H04L45/74 ,  H04L45/34 ,  H04L45/58 ,  H04L45/60 ,  H04L49/109 ,  H04L49/70

Abstract: A router includes a plurality of virtual networks, a plurality of output links, at least one decoder and arbitration circuitry. Each virtual network has a plurality of virtual network inputs and a plurality of virtual network outputs. Each virtual network output is associated with an output link. The decoder decodes a header of a data unit received on a virtual network of one of the virtual network inputs. The decoder generates a first request and a second request. The first request is for the allocation of a virtual network output of the virtual network to the virtual network input. The second request is for the allocation of an output link associated with the virtual network output to the virtual network output. The arbitration circuitry performs arbitration of the first request and arbitration of the second request in parallel.

Abstract translation: 路由器包括多个虚拟网络，多个输出链路，至少一个解码器和仲裁电路。 每个虚拟网络具有多个虚拟网络输入和多个虚拟网络输出。 每个虚拟网络输出与输出链路相关联。 解码器解码在虚拟网络输入之一的虚拟网络上接收的数据单元的报头。 解码器产生第一请求和第二请求。 第一个请求是将虚拟网络的虚拟网络输出分配给虚拟网络输入。 第二个请求是将与虚拟网络输出相关联的输出链路分配给虚拟网络输出。 仲裁电路并行执行第一请求的仲裁和第二请求的仲裁。

公开(公告)号：US20130136129A1

公开(公告)日：2013-05-30

申请号：US13673505

申请日：2012-11-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Riccardo Locatelli ,  Esa Petri ,  Antonio-Marcello Coppolla ,  Luca Fanucci ,  Sergio Saponara ,  Tony Bacchillone

IPC: H04L12/56

CPC classification number: H04L45/74 ,  H04L45/34 ,  H04L45/58 ,  H04L45/60 ,  H04L49/109 ,  H04L49/70

Abstract: A router includes a plurality of virtual networks, a plurality of output links, at least one decoder and arbitration circuitry. Each virtual network has a plurality of virtual network inputs and a plurality of virtual network outputs. Each virtual network output is associated with an output link. The decoder decodes a header of a data unit received on a virtual network of one of the virtual network inputs. The decoder generates a first request and a second request. The first request is for the allocation of a virtual network output of the virtual network to the virtual network input. The second request is for the allocation of an output link associated with the virtual network output to the virtual network output. The arbitration circuitry performs arbitration of the first request and arbitration of the second request in parallel.

Abstract translation: 路由器包括多个虚拟网络，多个输出链路，至少一个解码器和仲裁电路。 每个虚拟网络具有多个虚拟网络输入和多个虚拟网络输出。 每个虚拟网络输出与输出链路相关联。 解码器解码在虚拟网络输入之一的虚拟网络上接收的数据单元的报头。 解码器产生第一请求和第二请求。 第一个请求是将虚拟网络的虚拟网络输出分配给虚拟网络输入。 第二个请求是将与虚拟网络输出相关联的输出链路分配给虚拟网络输出。 仲裁电路并行执行第一请求的仲裁和第二请求的仲裁。