DEVICE WITH A PLURALITY OF CLOCK DOMAINS
    1.
    发明申请

    公开(公告)号:US20200379506A1

    公开(公告)日:2020-12-03

    申请号:US16879535

    申请日:2020-05-20

    Abstract: In an embodiment a device includes a first circuit configured to send a signal comprising numbers successively separated by a constant value to at least one second circuit, each second circuit being in a clock domain different from a clock domain of the first circuit and at least one third circuit configured to determine whether the successive numbers of the signal received by the second circuit are separated by the constant value, wherein the signal is sent to a respective third circuit in each of the clock domains different from the clock domain of the first circuit.

    Device with a plurality of clock domains

    公开(公告)号:US11416022B2

    公开(公告)日:2022-08-16

    申请号:US16879535

    申请日:2020-05-20

    Abstract: In an embodiment a device includes a first circuit configured to send a signal comprising numbers successively separated by a constant value to at least one second circuit, each second circuit being in a clock domain different from a clock domain of the first circuit and at least one third circuit configured to determine whether the successive numbers of the signal received by the second circuit are separated by the constant value, wherein the signal is sent to a respective third circuit in each of the clock domains different from the clock domain of the first circuit.

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