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Patent Agency Ranking
公开(公告)号：US11281807B2
公开(公告)日：2022-03-22
申请号：US16403275
申请日：2019-05-03
Inventor： Rosalino Critelli , Giuseppe Guarnaccia , Delphine Le-Goascoz , Nicolas Anquet
Abstract: In one example, an integrated circuit includes a register interface that includes a plurality of registers, a bus interface configured to monitor write requests transmitted to the register interface, where the write requests include a target address and data to be written. The bus interface is configured to receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers. The integrated circuit includes a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid.
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公开(公告)号：US20190354726A1
公开(公告)日：2019-11-21
申请号：US16403275
申请日：2019-05-03
Inventor： Rosalino Critelli , Giuseppe Guarnaccia , Delphine Le-Goascoz , Nicolas Anquet
Abstract: In one example, an integrated circuit includes a register interface that includes a plurality of registers, a bus interface configured to monitor write requests transmitted to the register interface, where the write requests include a target address and data to be written. The bus interface is configured to receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers. The integrated circuit includes a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid.
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3.发明授权公开(公告)号：US11698993B2
公开(公告)日：2023-07-11
申请号：US17161544
申请日：2021-01-28
Inventor： Gilles Pelissier , Nicolas Anquet , Delphine Le-Goascoz
CPC classification number: G06F21/72 , H04L9/06 , H04L9/0866 , G06F2221/2113
Abstract: A unique hardware key is recorded a secure hardware environment. A first logic circuit of the secure hardware environment is configured to generate a unique derived key from said unique hardware key and at least one piece of information. The at least one piece of information relates to one or more of an execution context and a use of a secret key. The secure hardware environment further includes a first encryption device that performs a symmetric encryption of the secret key using the unique derived key. This symmetric encryption generates an encrypted secret key for use outside of the secure hardware environment.
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公开(公告)号：US11610025B2
公开(公告)日：2023-03-21
申请号：US17161194
申请日：2021-01-28
Inventor： Gilles Pelissier , Nicolas Anquet , Delphine Le-Goascoz
Abstract: An integrated circuit includes a secure hardware environment having a first input that receives a key number. A key generation device generates a secret key from the key number and a unique key. A signature generation device generates a signature associated with the key number. A second input of the secure hardware environment receives encrypted binary data. A decryption device operates to decrypt the received encrypted binary data using the secret key. A third input the secure hardware environment receives an authentication signature. An authentication device authorizes use of the secret key to decrypt only if the signature generated by the signature generation device is identical to the authentication signature.
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公开(公告)号：US20190179773A1
公开(公告)日：2019-06-13
申请号：US16207817
申请日：2018-12-03
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Dragos Davidescu , Nicolas Anquet
Abstract: A method for writing a set of information for processing by a processing unit of an integrated circuit in an external memory outside the integrated circuit, includes: generating, within the integrated circuit, an encryption key; for each item of information intended to be written at an address of the external memory, first encrypting the address within the integrated circuit by a first encryption/decryption circuit using the encryption key to obtain an encrypted address; second encrypting the item of information within the integrated circuit using a second encryption/decryption circuit using the encrypted address to obtain an encrypted item of information; and writing the encrypted item of information at the address of the external memory, wherein the external memory is not able to be written twice at a same address during a write process
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