公开(公告)号：US11143701B2

公开(公告)日：2021-10-12

申请号：US16909696

申请日：2020-06-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Lionel Sinegre ,  Eric Sagnard ,  Stephan Courcambeck ,  William Orlando ,  Layachi Daineche

IPC: G01R31/00 ,  G01R31/317 ,  G06F11/22 ,  G06F9/4401 ,  G06F11/36 ,  G06F21/75 ,  G06F21/62

Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

公开(公告)号：US10705141B2

公开(公告)日：2020-07-07

申请号：US16155953

申请日：2018-10-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Lionel Sinegre ,  Eric Sagnard ,  Stephan Courcambeck ,  William Orlando ,  Layachi Daineche

IPC: G01R31/00 ,  G01R31/317 ,  G06F11/22 ,  G06F9/4401 ,  G06F11/36 ,  G06F21/75 ,  G06F21/62

Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

公开(公告)号：US20200319247A1

公开(公告)日：2020-10-08

申请号：US16909696

申请日：2020-06-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Lionel Sinegre ,  Eric Sagnard ,  Stephan Courcambeck ,  William Orlando ,  Layachi Daineche

IPC: G01R31/317 ,  G06F11/22 ,  G06F9/4401 ,  G06F11/36 ,  G06F21/75 ,  G06F21/62

Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

公开(公告)号：US20190107576A1

公开(公告)日：2019-04-11

申请号：US16155953

申请日：2018-10-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Lionel Sinegre ,  Eric Sagnard ,  Stephan Courcambeck ,  William Orlando ,  Layachi Daineche

IPC: G01R31/317 ,  G06F11/36 ,  G06F9/4401 ,  G06F11/22

Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.