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公开(公告)号:US10135625B2
公开(公告)日:2018-11-20
申请号:US14984073
申请日:2015-12-30
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Yvon Bahout
Abstract: A method of communication between a first circuit and a second circuit coupled together over a two-line bus having a clock line and a data line. A power signal is provided to the second circuit over the two-line bus by setting the clock line and the data line to different potential levels. A bit is transmitted from one of the first circuit and the second circuit to the other of the first circuit and the second circuit by setting the data line to a potential level according to a state of the bit to be transmitted when the clock line is set at a first potential level. A bit is read in response to a transition of the clock line from the first potential level to a second potential level, different from the first potential level.
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公开(公告)号:US20160344563A1
公开(公告)日:2016-11-24
申请号:US14984073
申请日:2015-12-30
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Yvon Bahout
IPC: H04L12/10
CPC classification number: H04L12/10 , G06F13/4291
Abstract: A method of communication between a first circuit and a second circuit coupled together over a two-line bus having a clock line and a data line. A power signal is provided to the second circuit over the two-line bus by setting the clock line and the data line to different potential levels. A bit is transmitted from one of the first circuit and the second circuit to the other of the first circuit and the second circuit by setting the data line to a potential level according to a state of the bit to be transmitted when the clock line is set at a first potential level. A bit is read in response to a transition of the clock line from the first potential level to a second potential level, different from the first potential level.
Abstract translation: 一种通过具有时钟线和数据线的双线总线耦合在一起的第一电路和第二电路之间的通信方法。 通过将时钟线和数据线设置为不同的电位电平,通过双线总线将电源信号提供给第二电路。 将第一电路和第二电路中的一个发送到第一电路和第二电路中的另一个,通过根据当设置时钟线时要发送的位的状态将数据线设置为电位电平 处于第一潜在水平。 响应于时钟线从第一电位电平到不同于第一电位电平的第二电位电平而读取一位。
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