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公开(公告)号：US20230006684A1
公开(公告)日：2023-01-05
申请号：US17807452
申请日：2022-06-17
摘要： In an embodiment a method includes generating a low-frequency clock signal having a first frequency, in a standby mode and in a run mode of the CPU, generating a high-frequency clock signal having a second frequency higher than the first frequency, in the run mode, updating a value of the reference time base at each period of the low-frequency clock signal in the standby mode, and accessing the counter register with the high-frequency clock signal in the run mode.
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公开(公告)号：US12081224B2
公开(公告)日：2024-09-03
申请号：US17807452
申请日：2022-06-17
CPC分类号： H03L7/24 , G06F1/14 , G06F9/4812 , H03L7/0992
摘要： In an embodiment a method includes generating a low-frequency clock signal having a first frequency, in a standby mode and in a run mode of the CPU, generating a high-frequency clock signal having a second frequency higher than the first frequency, in the run mode, updating a value of the reference time base at each period of the low-frequency clock signal in the standby mode, and accessing the counter register with the high-frequency clock signal in the run mode.
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公开(公告)号：US11856080B2
公开(公告)日：2023-12-26
申请号：US18059784
申请日：2022-11-29
IPC分类号： H04L7/00
CPC分类号： H04L7/0012
摘要： A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.
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