公开(公告)号：US20140043718A1

公开(公告)日：2014-02-13

申请号：US14056698

申请日：2013-10-17

Applicant: STMicroelectronics (Tours) SAS ,  STMicroelectronics S.r.l.

Inventor： Vincent Caro ,  Davide Rodilosso

IPC: H01G7/06

CPC classification number: H01G7/06 ,  H01L21/31111 ,  H01L28/55

Abstract: The disclosure concerns a method for etching a PVD deposited barium strontium titanate layer, wherein a non-ionic surfactant at a concentration between 0.1 and 1 percent is added to an acid etching solution.

Abstract translation: 本公开涉及一种用于蚀刻PVD沉积的钛酸钡锶钡层的方法，其中将0.1至1％浓度的非离子表面活性剂加入到酸蚀刻溶液中。

公开(公告)号：US12230698B2

公开(公告)日：2025-02-18

申请号：US18110095

申请日：2023-02-15

Applicant: STMicroelectronics (Tours) SAS

Inventor： Patrick Hauttecoeur ,  Vincent Caro

IPC: H01L29/747 ,  H01L29/06 ,  H01L29/66

Abstract: A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.

公开(公告)号：US11610988B2

公开(公告)日：2023-03-21

申请号：US17188826

申请日：2021-03-01

Applicant: STMicroelectronics (Tours) SAS

Inventor： Patrick Hauttecoeur ,  Vincent Caro

IPC: H01L29/747 ,  H01L29/06 ,  H01L29/66

Abstract: A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.