公开(公告)号：US12230698B2

公开(公告)日：2025-02-18

申请号：US18110095

申请日：2023-02-15

Applicant: STMicroelectronics (Tours) SAS

Inventor： Patrick Hauttecoeur ,  Vincent Caro

IPC: H01L29/747 ,  H01L29/06 ,  H01L29/66

Abstract: A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.

公开(公告)号：US20240204112A1

公开(公告)日：2024-06-20

申请号：US18593490

申请日：2024-03-01

Applicant: STMicroelectronics (Tours) SAS

Inventor： Arnaud YVON ,  Lionel JAOUEN

IPC: H01L29/861 ,  H01L21/761 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/8611 ,  H01L21/761 ,  H01L29/0623 ,  H01L29/66128 ,  H01L29/66136

Abstract: A device includes a diode. The anode of the diode includes first, second, and third areas. The first area partially covers the second area and has a forst doping level greater than a second doping level of the second area. The second area partially covers the third area and has the second doping level greater than a third doping level of the third area. A first insulating layer partially overlaps the first and second areas.

公开(公告)号：US20240063162A1

公开(公告)日：2024-02-22

申请号：US18497691

申请日：2023-10-30

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier ORY ,  Christophe LEBRERE

IPC: H01L23/00 ,  H01L25/10

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/11916 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2224/8185

Abstract: The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 μm, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.

公开(公告)号：US11869959B2

公开(公告)日：2024-01-09

申请号：US17412556

申请日：2021-08-26

Applicant: STMicroelectronics (Tours) SAS

Inventor： Frederic Gautier

IPC: H02M3/335 ,  H01L29/739 ,  H01L27/07 ,  H01L29/872 ,  H03K17/74

CPC classification number: H01L29/7392 ,  H01L27/0727 ,  H01L29/8725 ,  H02M3/33592 ,  H03K17/74

Abstract: A device includes a controllable current source connected between a first node and a first terminal coupled to a cathode of a controllable diode. A capacitor is connected between the first node and a second terminal coupled to an anode of the controllable diode. A first switch is connected between the first node and a third terminal coupled to a gate of the controllable diode. A second switch is connected between the second and third terminals. A first diode is connected between the third terminal and the second terminal, an anode of the first diode being preferably coupled to the third terminal.

公开(公告)号：US11721830B2

公开(公告)日：2023-08-08

申请号：US15790529

申请日：2017-10-23

Applicant: STMicroelectronics (Tours) SAS

Inventor： Severin Larfaillou ,  Delphine Guy-Bouyssou

IPC: H01M10/052 ,  H01M10/44 ,  H01M10/0585 ,  H01M4/38 ,  H01M4/40 ,  H01M4/04 ,  H01M4/134 ,  H01M4/1395 ,  H01M10/0562

CPC classification number: H01M10/052 ,  H01M4/0445 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/38 ,  H01M4/405 ,  H01M10/0562 ,  H01M10/0585 ,  H01M10/44 ,  H01M4/382

Abstract: A thin-film lithium ion battery includes a negative electrode layer, a positive electrode layer, an electrolyte layer disposed between the positive and negative electrode layers, and a lithium layer with lithium pillars extending therefrom formed in the negative electrode layer adjoining the electrolyte layer.

公开(公告)号：US20220416053A1

公开(公告)日：2022-12-29

申请号：US17899071

申请日：2022-08-30

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Samuel MENARD

IPC: H01L29/47 ,  H01L29/73 ,  H01L29/747 ,  H01L29/74 ,  H01L29/732 ,  H01L29/417

Abstract: A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.

公开(公告)号：US11462624B2

公开(公告)日：2022-10-04

申请号：US16230137

申请日：2018-12-21

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Samuel Menard

IPC: H01L29/00 ,  H01L29/47 ,  H01L29/73 ,  H01L29/747 ,  H01L29/74 ,  H01L29/732 ,  H01L29/417 ,  H01L29/45

Abstract: A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.

公开(公告)号：US20220271030A1

公开(公告)日：2022-08-25

申请号：US17741900

申请日：2022-05-11

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Mohamed BOUFNICHEL

IPC: H01L27/08 ,  H01L27/06 ,  H01L49/02

Abstract: The present disclosure concerns an integrated circuit comprising a substrate, the substrate comprising a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the circuit comprising a three-dimensional capacitor formed inside and on top of the first region, and at least first and second connection terminals formed on the second region, the first and second connection terminals being respectively connected to first and second electrodes of the three-dimensional capacitor.

公开(公告)号：US11380486B2

公开(公告)日：2022-07-05

申请号：US16571738

申请日：2019-09-16

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mohamed Boufnichel

IPC: H01L49/02 ,  H01G4/33 ,  H01G4/30 ,  H01G4/224

Abstract: A vertical capacitor includes a stack of layers conformally covering walls of a first material. The walls extend from a substrate made of a second material different from the first material.

公开(公告)号：US11362204B2

公开(公告)日：2022-06-14

申请号：US16706201

申请日：2019-12-06

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard ,  Lionel Jaouen

IPC: H01L29/74 ,  H01L29/749 ,  H01L29/06 ,  H01L29/08

Abstract: A thyristor is formed from a vertical stack of first, second, third, and fourth semiconductor regions of alternated conductivity types. The fourth semiconductor region is interrupted in a gate area of the thyristor. The fourth semiconductor region is further interrupted in a continuous corridor that extends longitudinally from the gate area towards an outer lateral edge of the fourth semiconductor region. A gate metal layer extends over the gate area of the thyristor. A cathode metal layer extends over the fourth semiconductor region but not over the continuous corridor.