System on a chip and a power down process for IP access resilience

    公开(公告)号:US11907156B2

    公开(公告)日:2024-02-20

    申请号:US17457553

    申请日:2021-12-03

    CPC classification number: G06F15/7807 G06F1/08 G06F1/14

    Abstract: According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.

    SYSTEM ON A CHIP AND PROCESS FOR TRANSACTION

    公开(公告)号:US20220179822A1

    公开(公告)日:2022-06-09

    申请号:US17457553

    申请日:2021-12-03

    Abstract: According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.

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