公开(公告)号：US20180268895A1

公开(公告)日：2018-09-20

申请号：US15988140

申请日：2018-05-24

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Vivek Asthana ,  Naveen Batra

IPC: G11C11/419 ,  G11C7/12 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/12

Abstract: A method of operating a memory device includes providing a first voltage to a memory array, providing a second voltage to a peripheral logic circuit, receiving an access request, and in response to the access request, increasing a third voltage of a bit line of the memory array during a precharge phase.

公开(公告)号：US10008258B2

公开(公告)日：2018-06-26

申请号：US15296567

申请日：2016-10-18

Applicant: STMicroelectronics International N.V

Inventor： Piyush Jain ,  Vivek Asthana ,  Naveen Batra

IPC: G11C11/419 ,  G11C7/12 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/12

Abstract: A circuit can be used, for example, with a multi-supply memory device. The circuit includes a first conductor and a second conductor. A first transistor has a current path coupled between the first conductor and the second conductor. A second transistor also has a current path coupled between the first conductor and the second conductor. A pulse generator circuit has an input coupled to a control terminal of the first transistor and an output coupled to a control terminal of the second transistor.

公开(公告)号：US09508405B2

公开(公告)日：2016-11-29

申请号：US14045589

申请日：2013-10-03

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Vivek Asthana ,  Naveen Batra

IPC: G11C7/12 ,  G11C11/419 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/12

Abstract: A method and apparatus for operating a memory device with wider difference in array and periphery voltage is presented. The memory device includes a bit line, a complementary bit line, a memory cell, a first pre-charge circuit, and a second pre-charge circuit. The memory cell, the first pre-charge circuit, and the second pre-charge circuit are coupled between the bit line and the complementary bit line. The first pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a first voltage level. The second pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a second voltage level that is different than the first voltage level. In some examples, two precharge circuits are configured to operate such that memory access is ensured to be static noise margin safe even under wider difference between two voltage levels.

Abstract translation: 提出了一种用于操作阵列和外围电压差较大的存储器件的方法和装置。 存储器件包括位线，互补位线，存储单元，第一预充电电路和第二预充电电路。 存储单元，第一预充电电路和第二预充电电路耦合在位线和互补位线之间。 第一预充电电路被配置为将位线和互补位线预充电到第一电压电平。 第二预充电电路被配置为将位线和互补位线预充电到不同于第一电压电平的第二电压电平。 在一些示例中，两个预充电电路被配置为操作，使得即使在两个电压电平之间的较大差异下，也能确保存储器存取是静态噪声容限。

公开(公告)号：US10468095B2

公开(公告)日：2019-11-05

申请号：US15988140

申请日：2018-05-24

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Vivek Asthana ,  Naveen Batra

IPC: G11C7/12 ,  G11C11/419 ,  G11C5/14

Abstract: A method of operating a memory device includes providing a first voltage to a memory array, providing a second voltage to a peripheral logic circuit, receiving an access request, and in response to the access request, increasing a third voltage of a bit line of the memory array during a precharge phase.

公开(公告)号：US08917561B2

公开(公告)日：2014-12-23

申请号：US14289072

申请日：2014-05-28

Applicant: STMicroelectronics International N.V.

Inventor： Vivek Asthana

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C11/417

Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.