公开(公告)号：US09311990B1

公开(公告)日：2016-04-12

申请号：US14573106

申请日：2014-12-17

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Piyush Jain

IPC: G11C11/40 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/1045 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/418

Abstract: A pseudo dual port memory includes a set of dual port memory cells having a read port and a write port, and configured to store data words in each of a plurality of addressed locations, and a set of single port memory cells having a read/write port, and configured to store data words in each of a plurality of addressed locations. A valid data storage unit is configured to store valid bits corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells. Control circuitry is configured to access the addressed locations of the set of dual port memory cells and the set of single port memory cells. The control circuitry performs a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and updates corresponding valid bits in the valid data storage unit, and performs a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.

Abstract translation: 伪双端口存储器包括具有读端口和写端口的一组双端口存储器单元，并且被配置为在多个寻址位置的每一个中存储数据字，以及一组具有读/写的单端口存储器单元 并且被配置为将数据字存储在多个寻址位置的每一个中。 有效数据存储单元被配置为存储对应于该组双端口存储器单元和该组单端口存储器单元的寻址位置的有效位。 控制电路被配置为访问该组双端口存储器单元和一组单端口存储器单元的寻址位置。 控制电路使用该组双端口存储单元的写入端口和一组单端口存储器单元的读/写端口执行同时写入操作，并更新有效数据存储单元中的对应的有效位，并且执行 在双端口存储单元集合和单端口存储单元集合的相同寻址位置处使用双端口存储单元组的读端口和单端口集合的读/写端口进行并行读操作 并且基于有效数据存储单元中的相应的有效位来确定哪个存储的数据字是有效的。

公开(公告)号：US09524242B2

公开(公告)日：2016-12-20

申请号：US14166003

申请日：2014-01-28

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Harsh Rawat ,  Gangaikondan Subramani Visweswaran

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F2212/6032

Abstract: A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read.

Abstract translation: 缓存包括多个高速缓存路径，每个高速缓存路径具有标签存储器字段和对应的数据字段。 通过由读取存储器地址（读取标签部分和读取索引部分）和写入存储器地址（写入标签部分和写入索引部分）定义的同时读取操作，高速缓存确定读取高速缓存命中并从一种高速缓存读取 如读取的存储器地址的读取标签和索引部分所示。 此外，确定写入存储器地址的写入标签和索引部分所指示的写入是否将以与读取相同的一种高速缓存方式进行，以便被冲突。 如果存在这样的冲突，则写入将与读取到一个缓存方式同时实现到与用于读取的不同的缓存方式。

公开(公告)号：US09508405B2

公开(公告)日：2016-11-29

申请号：US14045589

申请日：2013-10-03

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Vivek Asthana ,  Naveen Batra

IPC: G11C7/12 ,  G11C11/419 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/12

Abstract: A method and apparatus for operating a memory device with wider difference in array and periphery voltage is presented. The memory device includes a bit line, a complementary bit line, a memory cell, a first pre-charge circuit, and a second pre-charge circuit. The memory cell, the first pre-charge circuit, and the second pre-charge circuit are coupled between the bit line and the complementary bit line. The first pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a first voltage level. The second pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a second voltage level that is different than the first voltage level. In some examples, two precharge circuits are configured to operate such that memory access is ensured to be static noise margin safe even under wider difference between two voltage levels.

Abstract translation: 提出了一种用于操作阵列和外围电压差较大的存储器件的方法和装置。 存储器件包括位线，互补位线，存储单元，第一预充电电路和第二预充电电路。 存储单元，第一预充电电路和第二预充电电路耦合在位线和互补位线之间。 第一预充电电路被配置为将位线和互补位线预充电到第一电压电平。 第二预充电电路被配置为将位线和互补位线预充电到不同于第一电压电平的第二电压电平。 在一些示例中，两个预充电电路被配置为操作，使得即使在两个电压电平之间的较大差异下，也能确保存储器存取是静态噪声容限。

公开(公告)号：US20150212945A1

公开(公告)日：2015-07-30

申请号：US14166003

申请日：2014-01-28

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Harsh Rawat ,  Gangaikondan Subramani Visweswaran

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F2212/6032

Abstract: A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read.

Abstract translation: 缓存包括多个高速缓存路径，每个高速缓存路径具有标签存储器字段和对应的数据字段。 通过由读取存储器地址（读取标签部分和读取索引部分）和写入存储器地址（写入标签部分和写入索引部分）定义的同时读取操作，高速缓存确定读取高速缓存命中并从一种高速缓存读取 如读取的存储器地址的读取标签和索引部分所示。 此外，确定写入存储器地址的写入标签和索引部分所指示的写入是否将以与读取相同的一种高速缓存方式进行，以便被冲突。 如果存在这样的冲突，则写入将与读取到一个缓存方式同时实现到与用于读取的不同的缓存方式。

公开(公告)号：US20180268895A1

公开(公告)日：2018-09-20

申请号：US15988140

申请日：2018-05-24

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Vivek Asthana ,  Naveen Batra

IPC: G11C11/419 ,  G11C7/12 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/12

Abstract: A method of operating a memory device includes providing a first voltage to a memory array, providing a second voltage to a peripheral logic circuit, receiving an access request, and in response to the access request, increasing a third voltage of a bit line of the memory array during a precharge phase.

公开(公告)号：US10008258B2

公开(公告)日：2018-06-26

申请号：US15296567

申请日：2016-10-18

Applicant: STMicroelectronics International N.V

Inventor： Piyush Jain ,  Vivek Asthana ,  Naveen Batra

IPC: G11C11/419 ,  G11C7/12 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/12

Abstract: A circuit can be used, for example, with a multi-supply memory device. The circuit includes a first conductor and a second conductor. A first transistor has a current path coupled between the first conductor and the second conductor. A second transistor also has a current path coupled between the first conductor and the second conductor. A pulse generator circuit has an input coupled to a control terminal of the first transistor and an output coupled to a control terminal of the second transistor.

公开(公告)号：US10468095B2

公开(公告)日：2019-11-05

申请号：US15988140

申请日：2018-05-24

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Vivek Asthana ,  Naveen Batra

IPC: G11C7/12 ,  G11C11/419 ,  G11C5/14

Abstract: A method of operating a memory device includes providing a first voltage to a memory array, providing a second voltage to a peripheral logic circuit, receiving an access request, and in response to the access request, increasing a third voltage of a bit line of the memory array during a precharge phase.