公开(公告)号：US09891279B2

公开(公告)日：2018-02-13

申请号：US13919884

申请日：2013-06-17

Applicant: STMicroelectronics International N.V.

Inventor： Ajay Kumar Dimri

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/31726 ,  G01R31/318552

Abstract: An apparatus has a large block of synchronous logic arranged to include a first partition and a second partition. The first partition is configured to receive a first clock signal during a functional mode and during a test mode. The second partition is configured to receive the first clock signal during the functional mode, and the second partition configured to receive a second clock signal during a test mode. The second clock signal has the same frequency as the first clock signal. The second clock signal has a different phase from the first clock signal.

公开(公告)号：US20140372823A1

公开(公告)日：2014-12-18

申请号：US13919884

申请日：2013-06-17

Applicant: STMicroelectronics International N.V.

Inventor： Ajay Kumar Dimri

IPC: G01R31/317

CPC classification number: G01R31/31726 ,  G01R31/318552

Abstract: An apparatus has a large block of synchronous logic arranged to include a first partition and a second partition. The first partition is configured to receive a first clock signal during a functional mode and during a test mode. The second partition is configured to receive the first clock signal during the functional mode, and the second partition configured to receive a second clock signal during a test mode. The second clock signal has the same frequency as the first clock signal. The second clock signal has a different phase from the first clock signal.

Abstract translation: 一种装置具有大的同步逻辑块，其被布置成包括第一分区和第二分区。 第一分区被配置为在功能模式期间和测试模式期间接收第一时钟信号。 第二分区被配置为在功能模式期间接收第一时钟信号，并且第二分区被配置为在测试模式期间接收第二时钟信号。 第二时钟信号具有与第一时钟信号相同的频率。 第二时钟信号与第一时钟信号具有不同的相位。