公开(公告)号：US20130159802A1

公开(公告)日：2013-06-20

申请号：US13739799

申请日：2013-01-11

Applicant: STMicroelectronics International N.V.

Inventor： Swapnil BAHL ,  Akhil GARG

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318594

Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.

Abstract translation: 用于在集成电路（IC）中测试多时钟域的系统包括耦合到多个时钟控制器的多个时钟源。 每个时钟源产生与多时钟域之一相关联的快速时钟。 每个时钟控制器配置为提供捕获脉冲以测试一个时钟域。 提供给时钟域的捕获脉冲处于与时钟域相关联的快速时钟的频率。 时钟控制器依次操作以提供捕获脉冲来测试时钟域。