公开(公告)号：US20150323594A1

公开(公告)日：2015-11-12

申请号：US14270964

申请日：2014-05-06

Applicant: STMicroelectronics International N.V.

Inventor： Shray KHULLAR ,  Swapnil BAHL

IPC: G01R31/3177

CPC classification number: G01R31/31727 ,  G01R31/2815 ,  G01R31/31704 ,  G01R31/31705 ,  G01R31/3177 ,  G01R31/318552 ,  G01R31/318594

Abstract: The On-Chip Clock (OCC) circuit is for testing an integrated circuit having logic blocks connected in scan chains. An OCC controller is configured to receive a plurality of clock signals and output a plurality of shift/capture clock signals for use by the scan chains of logic blocks, the plurality of shift/capture clock signals including at least two consecutive at-speed capture clock pulses. An OCC monitor is configured to provide a verification of OCC operation based upon the at least two consecutive at-speed capture clock pulses. The OCC monitor may include a plurality of registers configured to provide delayed pulses based upon the at least two consecutive at-speed capture clock pulses, a counter configured to count differences between the delayed pulses, and an output register coupled to the counter and configured to provide a static data verification (e.g. output on an integrated circuit pad) for the test engineer.

Abstract translation: 片内时钟（OCC）电路用于测试具有连接在扫描链中的逻辑块的集成电路。 OCC控制器被配置为接收多个时钟信号并输出​​多个移位/捕获时钟信号以供逻辑块的扫描链使用，所述多个移位/捕获时钟信号包括至少两个连续的低速捕获时钟 脉冲。 OCC监视器被配置为基于至少两个连续的在线捕获时钟脉冲来提供对OCC操作的验证。 OCC监视器可以包括多个寄存器，其被配置为基于至少两个连续的在线捕获时钟脉冲提供延迟的脉冲，配置为对延迟的脉冲之间的差异进行计数的计数器，以及耦合到计数器的输出寄存器，并被配置为 为测试工程师提供静态数据验证（例如集成电路板上的输出）。

公开(公告)号：US20130159802A1

公开(公告)日：2013-06-20

申请号：US13739799

申请日：2013-01-11

Applicant: STMicroelectronics International N.V.

Inventor： Swapnil BAHL ,  Akhil GARG

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318594

Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.

Abstract translation: 用于在集成电路（IC）中测试多时钟域的系统包括耦合到多个时钟控制器的多个时钟源。 每个时钟源产生与多时钟域之一相关联的快速时钟。 每个时钟控制器配置为提供捕获脉冲以测试一个时钟域。 提供给时钟域的捕获脉冲处于与时钟域相关联的快速时钟的频率。 时钟控制器依次操作以提供捕获脉冲来测试时钟域。

公开(公告)号：US20150323593A1

公开(公告)日：2015-11-12

申请号：US14270935

申请日：2014-05-06

Applicant: STMicroelectronics International N.V.

Inventor： Swapnil BAHL ,  Shray Khullar

IPC: G01R31/3177

CPC classification number: G11C29/32 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318547 ,  G06F11/25 ,  G11C29/34 ,  G11C2029/3202

Abstract: An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.

Abstract translation: 具有扫描压缩架构的集成电路（IC）包括耦合在测试访问输入和耦合在一起以限定多个扫描路径的IC元件（例如，触发器）的块之间的解压缩逻辑。 IC元件的块包括在每个扫描路径的初始位置处的初始数据选择器，以及在至少一个扫描路径内的附加数据选择器下游，并且被配置为重新配置至少一个中的IC元件的顺序 扫描路径。 压缩逻辑耦合在IC元件块和测试访问输出之间。