公开(公告)号：US20240329125A1

公开(公告)日：2024-10-03

申请号：US18616929

申请日：2024-03-26

Applicant: STMicroelectronics International N.V.

Inventor： Moise AVOCI UGWIRI ,  Giuliano FILPI ,  Fabrice COSTE ,  Alex GRIMA ,  Pedro Jr Santos PERALTA

IPC: G01R31/28 ,  H01L23/00

CPC classification number: G01R31/2887 ,  H01L24/75 ,  H01L24/81 ,  G01R31/2896 ,  H01L2224/75745 ,  H01L2224/75756 ,  H01L2224/81136 ,  H01L2224/8118

Abstract: A method and apparatus for aligning electrical contact formations, such as bumps or solder balls, at a first surface of a Wafer Level Chip Scale Package (WLCSP) semiconductor device with electrically conductive pins in an array of electrically conductive pins such as “pogo” pins is provided. The semiconductor device includes, opposite the first surface, a second surface protected by a protection layer. The method includes aligning the semiconductor device to a first alignment member by exposing the protected second surface of the semiconductor device to a chamfered surface in the first alignment member. A second alignment member is aligned to the array of electrically conductive pins. The electrical contact formations are aligned with respect to the array of electrically conductive pins as desired in response to the first and second alignment members being mutually aligned, in response to the semiconductor device being “landed” onto the array of electrically conductive pins.