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1.发明申请公开(公告)号：US20180083602A1
公开(公告)日：2018-03-22
申请号：US15460520
申请日：2017-03-16
Inventor： Alok Kumar Tripathi , Amit Verma , Pascal Urard
CPC classification number: H03K3/356104 , H03K3/012 , H03K3/35625 , H03K19/0002
Abstract: A synchronous retention flip-flop circuit includes a first circuit module powered by an interruptible power source and a second circuit module powered by a permanent power source. The first circuit module includes a first latch circuit and a second latch circuit which are configured to store at least one datum while the interruptible power source is supplying power. A transmission circuit operates to deliver the at least one datum to the second circuit module before an interruption of the interruptible power source. The second circuit module preserves the at least one datum during the interruption. Following an end of the interruption, a restoring circuit transfers the at least one datum from the second circuit module to the first circuit module via a single one of the first and second latch circuits.
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公开(公告)号：US10153754B2
公开(公告)日：2018-12-11
申请号：US15460520
申请日：2017-03-16
Inventor： Alok Kumar Tripathi , Amit Verma , Pascal Urard
IPC: H03K3/012 , H03K3/356 , H03K19/00 , H03K3/3562
Abstract: A synchronous retention flip-flop circuit includes a first circuit module powered by an interruptible power source and a second circuit module powered by a permanent power source. The first circuit module includes a first latch circuit and a second latch circuit which are configured to store at least one datum while the interruptible power source is supplying power. A transmission circuit operates to deliver the at least one datum to the second circuit module before an interruption of the interruptible power source. The second circuit module preserves the at least one datum during the interruption. Following an end of the interruption, a restoring circuit transfers the at least one datum from the second circuit module to the first circuit module via a single one of the first and second latch circuits.
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Patent Agency Ranking
公开(公告)号：US10277207B1
公开(公告)日：2019-04-30
申请号：US15892308
申请日：2018-02-08
Applicant: STMicroelectronics International N.V.
Inventor： Alok Kumar Tripathi , Amit Verma , Anuj Grover , Deepak Kumar Bihani , Tanmoy Roy , Tanuj Agrawal
IPC: H03K3/00 , H03K3/3562 , G11C11/412
Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.
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4.发明授权Conditional pulse generator circuit for low power pulse triggered flip flop 有权条件脉冲发生器电路用于低功率脉冲触发触发器公开(公告)号：US09401715B1
公开(公告)日：2016-07-26
申请号：US14718204
申请日：2015-05-21
Applicant: STMicroelectronics International N.V.
Inventor： Alok Kumar Tripathi , Priyankar Mathuria
CPC classification number: H03K19/0013 , H03K3/012 , H03K3/356173
Abstract: An electronic device includes a pulsed latch circuit configured to latch a data input signal to an output based upon receipt of a pulse signal. A pulse generation circuit is configured to compare the data input signal and an output signal at the output of the pulsed latch circuit, and to generate the pulse signal based upon a mismatch therebetween in response to a clock signal.
Abstract translation: 电子设备包括脉冲锁存电路，其被配置为基于接收到脉冲信号将数据输入信号锁存到输出端。 脉冲发生电路被配置为将数据输入信号和脉冲锁存电路的输出端的输出信号进行比较，并且响应于时钟信号，基于它们之间的失配产生脉冲信号。
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公开(公告)号：US10585143B2
公开(公告)日：2020-03-10
申请号：US16031960
申请日：2018-07-10
Applicant: STMICROELECTRONICS SA , STMICROELECTRONICS (CROLLES 2) SAS , STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Pascal Urard , Florian Cacho , Vincent Huard , Alok Kumar Tripathi
IPC: G01R31/3183 , G01R31/3185 , G01R31/3177 , G01R31/317 , G01R31/3181 , G06F17/50
Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.
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公开(公告)号：US10263603B2
公开(公告)日：2019-04-16
申请号：US15462494
申请日：2017-03-17
Inventor： Pascal Urard , Alok Kumar Tripathi
IPC: H03K3/012 , H03K3/356 , H03K19/00 , H03K3/0233 , H03K3/3562
Abstract: The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.
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公开(公告)号：US20180083603A1
公开(公告)日：2018-03-22
申请号：US15462494
申请日：2017-03-17
Inventor： Pascal Urard , Alok Kumar Tripathi
CPC classification number: H03K3/356104 , H03K3/012 , H03K3/02335 , H03K3/35625 , H03K19/0002
Abstract: The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.
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