公开(公告)号：US20240422992A1

公开(公告)日：2024-12-19

申请号：US18738675

申请日：2024-06-10

Applicant: STMicroelectronics International N.V.

Inventor： Andrea REDAELLI

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00

Abstract: A memory circuit includes a memory array formed by electronic cells. Each electronic cell includes an integrated stack having, successively, a first electrode, an intermediate layer formed by an ovonic threshold switching layer, and a resistor connected to the intermediate layer. A control circuit is connected to the electronic cell. The control circuit is structured and configured to apply, between the first electrode and the resistor, a first voltage impulse of a first polarity to set a first logic state of the electronic cell and a second voltage impulse of a second polarity, opposite the first polarity, to set a second logic state of the electronic cell.

公开(公告)号：US20250048940A1

公开(公告)日：2025-02-06

申请号：US18228736

申请日：2023-08-01

Applicant: STMicroelectronics International N.V.

Inventor： Andrea REDAELLI ,  Luca LAURIN

IPC: H10N70/20 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00

Abstract: An in-memory computation (IMC) system includes an in-memory computation circuit formed by a first phase change memory (PCM) array configured to store the computational weights for an in-memory computation operation. A data storage circuit is formed by a second PCM array configured to store backup data for the computational weights for the in-memory computation operation. The first PCM array includes PCM cells made of a phase change material provided by a first GST alloy, and the second PCM array includes PCM cells made of a phase change material provided by a second GST alloy different from the first GST alloy. A control circuit operates to read the backup data from the second PCM array and write to the first PCM array to refresh the computational weights for the in-memory computation operation from the backup data.