公开(公告)号：US20250130550A1

公开(公告)日：2025-04-24

申请号：US18825669

申请日：2024-09-05

Applicant: STMicroelectronics International N.V.

Inventor： Donato Carpentieri ,  Daniele Mangano ,  Gianluca De Piano ,  Luigi Zaffarana

IPC: G05B19/4099

Abstract: A system-on-chip (SoC) including a memory is manufactured with a security feature configured to be enabled either in response to a set of SoC pads being asserted to respective security enablement values, or in response to a security key location in the memory having stored therein a key different from a security disablement key. During electrical wafer sorting (EWS), the security feature is disabled in response to a configuration of respective disablement values being applied to the set of SoC pads while, with the security feature disabled, the security key location in the memory is configured to have written therein a candidate disablement key. After EWS, the SoC pads are forced to respective non-transitory security enablement values wherein the security feature is enabled, and subsequent disablement of the security feature remains facilitated in response to the candidate disablement key being found to match the security disablement key.

公开(公告)号：US12294358B2

公开(公告)日：2025-05-06

申请号：US18409083

申请日：2024-01-10

Applicant: STMicroelectronics International N.V.

Inventor： Riccardo Condorelli ,  Antonino Mondello ,  Michele Alessandro Carrano ,  Daniele Mangano ,  Fabien Laplace ,  Luc Garcia ,  Michel Cuenca

IPC: H03K17/22 ,  G11C5/14

Abstract: A resettable digital stage operates when a supply voltage is higher than a threshold. A non-volatile memory stores a digital code read by a reading stage. A main power-on reset circuit generates a main reset signal controlling reset of the reading stage. A resettable volatile memory coupled to the reading stage stores a default value when reset. An auxiliary power-on reset circuit generates an auxiliary reset signal controlling reset of the volatile memory. Upon deactivation of the reset, the reading stage loads the digital code into the volatile memory. The main power-on reset circuit functions in a non-trimmed configuration response to the stored default value and in a trimmed configuration responsive to the stored digital code. The main power-on reset circuit has first and second operative thresholds which respectively fall within a first and second non-trimmed voltage range or within a first and second trimmed voltage range.