公开(公告)号：US20250130550A1

公开(公告)日：2025-04-24

申请号：US18825669

申请日：2024-09-05

Applicant: STMicroelectronics International N.V.

Inventor： Donato Carpentieri ,  Daniele Mangano ,  Gianluca De Piano ,  Luigi Zaffarana

IPC: G05B19/4099

Abstract: A system-on-chip (SoC) including a memory is manufactured with a security feature configured to be enabled either in response to a set of SoC pads being asserted to respective security enablement values, or in response to a security key location in the memory having stored therein a key different from a security disablement key. During electrical wafer sorting (EWS), the security feature is disabled in response to a configuration of respective disablement values being applied to the set of SoC pads while, with the security feature disabled, the security key location in the memory is configured to have written therein a candidate disablement key. After EWS, the SoC pads are forced to respective non-transitory security enablement values wherein the security feature is enabled, and subsequent disablement of the security feature remains facilitated in response to the candidate disablement key being found to match the security disablement key.