公开(公告)号：US20240321809A1

公开(公告)日：2024-09-26

申请号：US18601216

申请日：2024-03-11

Applicant: STMicroelectronics International N.V.

Inventor： Romain COFFY ,  David AUCHERE ,  Vipin VELAYUDHAN

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L24/27 ,  H01L24/29 ,  H01L2224/27318 ,  H01L2224/2741 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2924/151

Abstract: An integrated circuit chip is bonded to a support. The chip includes a first connection pad and two second connection pads. The support includes a third connection pad and two fourth connection pads. A stack layers includes first, second, and third conductive layers and insulating layers. The first, second, and third conductive layers are separated from one another by the insulating layers. The second conductive layer is positioned between the first and third conductive layers. The first and third conductive layers electrically connect the two second connection pads to the two fourth connection pads. The second conductive layer electrically connects the first connection pad to the third connection pad.