公开(公告)号：US11610612B2

公开(公告)日：2023-03-21

申请号：US17375149

申请日：2021-07-14

Applicant: STMicroelectronics International N.V.

Inventor： Ashish Kumar ,  Dipti Arya

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/14 ,  G11C8/08

Abstract: A row decoder includes decoder logic generating an initial word line signal, and two inverters. The first inverter is formed by a first p-channel transistor having a source coupled to a supply voltage and a gate receiving the initial word line signal. The second inverter is formed by a first n-channel transistor having a drain coupled to a drain of the first p-channel transistor, a source coupled to a shared ground line, and a gate receiving the initial word line signal. An inverse word line signal is generated at the drain of the first n-channel transistor. A second inverter inverts the inverse word line signal to produce a word line signal. Negative bias generation circuitry generates a negative bias voltage on the shared ground line when the initial word line signal is logic high, and otherwise couples the shared ground line to ground.