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    Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operation
    1.
    发明授权
    Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operation 有权

    公开(公告)号：US10224097B2

    公开(公告)日：2019-03-05

    申请号：US15909261

    申请日：2018-03-01

    Applicant: STMicroelectronics International N.V.

    Inventor： Ashish Kumar ,  Vinay Kumar ,  Kedar Janardan Dhori

    IPC: G11C11/419 ,  G11C11/418 ,  G11C5/14 ,  G11C5/06

    Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.

    Common-mode feedback for differential amplifier
    2.
    发明授权
    Common-mode feedback for differential amplifier 有权

    公开(公告)号：US10090815B2

    公开(公告)日：2018-10-02

    申请号：US15393713

    申请日：2016-12-29

    Applicant: STMicroelectronics International N.V

    Inventor： Ashish Kumar

    IPC: H03F1/34 ,  H03F3/45 ,  H03F1/02

    Abstract: An embodiment circuit includes an operational amplifier having a first output terminal and a second output terminal. The circuit further includes a detector coupled between the first output terminal and the second output terminal of the operational amplifier. The detector is configured to detect a common-mode output voltage at the first output terminal and the second output terminal of the operational amplifier. The circuit also includes a feedback amplifier having a first input terminal coupled to the detector and a second input terminal configured to receive a reference voltage. The feedback amplifier is configured to generate a feedback signal based on the common-mode output voltage and the reference voltage and to provide the feedback signal to the operational amplifier. The circuit additionally includes an impedance element having a first terminal coupled to the first input terminal of the feedback amplifier and a second terminal coupled to a supply voltage.

    High speed SRAM using enhance wordline/global buffer drive
    5.
    发明授权
    High speed SRAM using enhance wordline/global buffer drive 有权

    公开(公告)号：US11610612B2

    公开(公告)日：2023-03-21

    申请号：US17375149

    申请日：2021-07-14

    Applicant: STMicroelectronics International N.V.

    Inventor： Ashish Kumar ,  Dipti Arya

    IPC: G11C7/10 ,  G11C7/22 ,  G11C5/14 ,  G11C8/08

    Abstract: A row decoder includes decoder logic generating an initial word line signal, and two inverters. The first inverter is formed by a first p-channel transistor having a source coupled to a supply voltage and a gate receiving the initial word line signal. The second inverter is formed by a first n-channel transistor having a drain coupled to a drain of the first p-channel transistor, a source coupled to a shared ground line, and a gate receiving the initial word line signal. An inverse word line signal is generated at the drain of the first n-channel transistor. A second inverter inverts the inverse word line signal to produce a word line signal. Negative bias generation circuitry generates a negative bias voltage on the shared ground line when the initial word line signal is logic high, and otherwise couples the shared ground line to ground.

    Analog-to-digital converter with dynamic element matching
    6.
    发明授权
    Analog-to-digital converter with dynamic element matching 有权

    公开(公告)号：US09722623B1

    公开(公告)日：2017-08-01

    申请号：US15382813

    申请日：2016-12-19

    Applicant: STMicroelectronics International N.V.

    Inventor： Ashish Kumar ,  Chandrajit Debnath

    IPC: H03M1/34 ,  H03M1/46 ,  H03M1/12 ,  H03M1/06

    CPC classification number: H03M1/0665 ,  H03M3/464

    Abstract: An embodiment ADC device includes a plurality of comparator elements, each comparator element of the plurality of comparator elements having a first input connected to an input port, each comparator element of the plurality of comparator elements having a second input port connected to a reference signal port. The ADC device further has a switch matrix having routing circuitry connected to an output of each comparator of the plurality of comparators, and a plurality of latches, with each latch of the plurality of latches having an input connected to the routing circuitry. The routing circuitry is configured to connect the output of each comparator of the plurality of comparators to an input of each latch of the plurality of latches according to one or more signals received at one or more control ports.

    Reduced retention leakage SRAM
    9.
    发明授权
    Reduced retention leakage SRAM 有权

    公开(公告)号：US11145359B2

    公开(公告)日：2021-10-12

    申请号：US16809006

    申请日：2020-03-04

    Applicant: STMicroelectronics International N.V.

    Inventor： Ashish Kumar ,  Mohammad Aftab Alam

    IPC: G11C11/4099 ,  G11C5/14 ,  G11C11/413 ,  G11C11/4074

    Abstract: A memory device includes a memory array powered between a virtual supply and virtual ground nodes. A dummy memory array is powered between first and second nodes. A virtual supply generation circuit generates a virtual supply voltage at the virtual supply node as a function of a first control voltage. A virtual ground generation circuit generates a virtual ground at the virtual ground node as a function of a second control voltage. A first control voltage generation circuit coupled between the first node and a power supply voltage generates the first control voltage as tracking retention noise margin (RNM) of the memory array, the first control voltage falling as the RNM decreases. A second control voltage generation circuit coupled between the second node and ground generates the second control voltage as tracking RNM of the memory array, the second control voltage rising as the RNM decreases.

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