公开(公告)号：US12184277B2

公开(公告)日：2024-12-31

申请号：US18308215

申请日：2023-04-27

Applicant: STMicroelectronics International N.V.

Inventor： Giulia Colonna ,  Enea Dimroci

IPC: H03K19/00

Abstract: According to an embodiment, an integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

公开(公告)号：US20240364336A1

公开(公告)日：2024-10-31

申请号：US18308215

申请日：2023-04-27

Applicant: STMicroelectronics International N.V.

Inventor： Giulia Colonna ,  Enea Dimroci

IPC: H03K19/00 ,  G06F1/28

CPC classification number: H03K19/0016 ,  H03K19/0013

Abstract: According to an embodiment, an integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.