公开(公告)号：US20240320148A1

公开(公告)日：2024-09-26

申请号：US18188365

申请日：2023-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Loris LUISE ,  Fabio Giuseppe DE AMBROGGI

IPC: G06F12/06 ,  G06F13/16

CPC classification number: G06F12/063 ,  G06F13/1668 ,  G06F2212/254

Abstract: A system on chip (SoC) includes a CPU, a main bus, and a plurality of subsystems. The SoC also includes an address remapping module coupled between the CPU and the bus. The address remapping module quickly and efficiently changes any memory addresses that need to be changed with the CPU requests a read or write operation associated with the addresses.

公开(公告)号：US20220414420A1

公开(公告)日：2022-12-29

申请号：US17360986

申请日：2021-06-28

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Loris LUISE ,  Surinder Pal SINGH ,  Fabio Giuseppe DE AMBROGGI

IPC: G06N3/04 ,  G06F9/30 ,  G06F7/57

Abstract: Data structure and microcontroller architecture performing binary multiply-accumulate operations using multiple partial copies of weights. Destination-register location, source-register location, and weight-register location are received. Using the weight-register location, a sub-set of the weight bits is copied a select number of times based on a filter index value that is received. Each copy of the sub-set of weights is executed in parallel. Using the source-register location, a sub-set of the input bits is selected based on the size of the sub-set of weights, wherein the sub-set of input bits is shifted one bit from a previous sub-set of input bits. XOR operation is performed on each corresponding bit in the copy of the sub-set of weights with each corresponding bit in the selected sub-set of input bits. In a corresponding destination sub-location, output of each XOR operation is aggregated with each other and with current value of the corresponding destination sub-location.

公开(公告)号：US20180189229A1

公开(公告)日：2018-07-05

申请号：US15423272

申请日：2017-02-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Giuseppe DESOLI ,  Thomas BOESCH ,  Nitin CHAWLA ,  Surinder Pal SINGH ,  Elio GUIDETTI ,  Fabio Giuseppe DE AMBROGGI ,  Tommaso MAJO ,  Paolo Sergio ZAMBOTTI

IPC: G06F15/78 ,  G06N3/04 ,  G06F13/40

Abstract: Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.