公开(公告)号：US20240304731A1

公开(公告)日：2024-09-12

申请号：US18594210

申请日：2024-03-04

Applicant: STMicroelectronics International N.V.

Inventor： Francois TAILLIET ,  Marc BATTISTA

IPC: H01L29/8605 ,  H01L27/06

CPC classification number: H01L29/8605 ,  H01L27/0629

Abstract: An electronic device includes first and second diffused resistors in contact with each other to form a PN junction. The device is configured so that a potential difference between the first and second resistors is constant at any point of the PN junction. The PN junction is reverse-biased.

公开(公告)号：US20240170960A1

公开(公告)日：2024-05-23

申请号：US18512292

申请日：2023-11-17

Applicant: STMicroelectronics International N.V.

Inventor： Francois TAILLIET

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An ESD protection circuit includes a first voltage limiter having a first input terminal electrically coupled to each first signal pad of an integrated circuit by a first diode mounted in reverse bias during the integrated circuit operation. The first voltage limiter is mounted to be conductive between each first signal pad and ground during a positive ESD on the first signal pad. A second voltage limiter is electrically coupled and mounted to be conductive in the same direction as the first voltage limiter, between an external power supply pad and ground. An internal node outputs an internal power supply voltage to the domain, and is passed through by a current in response to a positive ESD on the power supply pad which is lower than the current passing through the first voltage limiter. A blocking diode is electrically connected between the first input terminal and the power supply pad.

公开(公告)号：US20240410932A1

公开(公告)日：2024-12-12

申请号：US18206192

申请日：2023-06-06

Applicant: STMicroelectronics International N.V.

Inventor： Francois TAILLIET

IPC: G01R31/26 ,  G01R19/165

Abstract: Disclosed herein is a detector circuit including a first detector configured to receive an input signal and generate a first detector output signal indicative of the input signal having reached a first activation threshold and a second detector configured to receive the input signal and, when enabled by the first detector output signal, generate a second detector output signal indicative of the input signal having reached a second activation threshold. A logic circuit is configured to perform a logical operation on the first and second detector output signals to generate an output indicative of the input signal having reached a voltage equal to the second activation threshold.