公开(公告)号：US20240332143A1

公开(公告)日：2024-10-03

申请号：US18429009

申请日：2024-01-31

Applicant: STMicroelectronics International N.V.

Inventor： Jing-En LUAN

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36

CPC classification number: H01L23/49558 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49513 ,  H01L23/49517 ,  H01L24/83 ,  H01L24/32 ,  H01L2224/32245 ,  H01L2224/83

Abstract: A hybrid QFN package includes an encapsulant body that encapsulates a lead frame and integrated circuit (IC) device where the lead frame includes a die pad and vertically offset leads. Back sides of the die pad and encapsulant body are coplanar at first surface. Front sides of the leads, the IC device and the encapsulant body are substantially coplanar at a second surface. An insulating layer covers the second surface except at a portion of the leads located at the peripheral edge of the encapsulating body. Vias extend through the insulating layer to the leads and IC device. Wiring lines on the insulating layer interconnect the vias. A passivation layer covers the wiring lines and vias.

公开(公告)号：US20240290807A1

公开(公告)日：2024-08-29

申请号：US18415231

申请日：2024-01-17

Applicant: STMicroelectronics International N.V.

Inventor： Jing-En LUAN

IPC: H01L27/146 ,  H01L23/31

CPC classification number: H01L27/14625 ,  H01L23/3171 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/14685

Abstract: A body of laser direct structuring (LDS) encapsulating material encapsulates an integrated circuit device and an optical element mounted thereto. Laser activated trace regions and via openings at a first surface of the body are plated to form first conductive lines and first conductive vias. A first passivation layer covers the first conductive lines, the first surface of the body and a portion of the optical element. A second passivation layer covers a thinned backside of the body and integrated circuit device where distal ends of the first conductive vias are exposed. A redistribution layer (RDL) at the second passivation layer includes second conductive lines, pads, and second conductive vias which extend through the second passivation layer to electrically connect the second conductive lines to the distal ends of the first conductive vias. A solder mask layer on the second passivation layer includes openings at the pads of the RDL.