公开(公告)号：US09236140B2

公开(公告)日：2016-01-12

申请号：US14014224

申请日：2013-08-29

Applicant: STMicroelectronics International N.V.

Inventor： Jitendra Dasani

IPC: G11C17/00 ,  G11C17/08 ,  H01L27/112 ,  G11C7/06 ,  G11C17/12

CPC classification number: G11C17/08 ,  G11C7/065 ,  G11C17/12 ,  H01L27/11226

Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.