Area optimized driver layout
    1.
    发明授权
    Area optimized driver layout 有权
    区域优化驱动程序布局

    公开(公告)号:US09268894B2

    公开(公告)日:2016-02-23

    申请号:US14279587

    申请日:2014-05-16

    CPC classification number: G06F17/5072 G06F17/5068 G06F17/5077

    Abstract: A computerized method for designing a layout of a driver includes analyzing a schematic circuit. PMOSFETs coupled between first common nodes are grouped into one or more first classes. NMOSFETs coupled between second common nodes are grouped into one or more second classes. The method further includes generating the layout for each MOSFET at each location in a layout area of the driver by generating a super parameterized cell (PCELL) layout block comprising a master MOSFET PCELL and a master guard ring PCELL for each of the first class and the second class. The master MOSFET PCELL includes a first set of parameters for the MOSFET and the master guard ring PCELL includes a second set of parameters for the guard ring around the MOSFET. A child PCELL of the master MOSFET PCELL and the master guard ring PCELL are instantiated at each location in the layout area.

    Abstract translation: 用于设计驱动器布局的计算机化方法包括分析原理图电路。 耦合在第一公共节点之间的PMOSFET被分组成一个或多个第一类。 耦合在第二公共节点之间的NMOSFET被分组成一个或多个第二类。 该方法还包括通过生成包括主MOSFET PCELL和主保护环PCELL的超参数化单元(PCELL)布局块来为驱动器的布局区域中的每个位置处的每个MOSFET生成布局,用于第一类和 二等。 主MOSFET PCELL包括MOSFET的第一组参数,主保护环PCELL包括围绕MOSFET的保护环的第二组参数。 主MOSFET PCELL和主保护环PCELL的子PCELL在布局区域的每个位置实例化。

    Area Optimized Driver Layout
    2.
    发明申请
    Area Optimized Driver Layout 有权
    区域优化驱动程序布局

    公开(公告)号:US20150331985A1

    公开(公告)日:2015-11-19

    申请号:US14279587

    申请日:2014-05-16

    CPC classification number: G06F17/5072 G06F17/5068 G06F17/5077

    Abstract: A computerized method for designing a layout of a driver includes analyzing a schematic circuit. PMOSFETs coupled between first common nodes are grouped into one or more first classes. NMOSFETs coupled between second common nodes are grouped into one or more second classes. The method further includes generating the layout for each MOSFET at each location in a layout area of the driver by generating a super parameterized cell (PCELL) layout block comprising a master MOSFET PCELL and a master guard ring PCELL for each of the first class and the second class. The master MOSFET PCELL includes a first set of parameters for the MOSFET and the master guard ring PCELL includes a second set of parameters for the guard ring around the MOSFET. A child PCELL of the master MOSFET PCELL and the master guard ring PCELL are instantiated at each location in the layout area.

    Abstract translation: 用于设计驱动器布局的计算机化方法包括分析原理图电路。 耦合在第一公共节点之间的PMOSFET被分组成一个或多个第一类。 耦合在第二公共节点之间的NMOSFET被分组成一个或多个第二类。 该方法还包括通过生成包括主MOSFET PCELL和主保护环PCELL的超参数化单元(PCELL)布局块来为驱动器的布局区域中的每个位置处的每个MOSFET生成布局,用于第一类和 二等。 主MOSFET PCELL包括MOSFET的第一组参数,主保护环PCELL包括围绕MOSFET的保护环的第二组参数。 主MOSFET PCELL和主保护环PCELL的子PCELL在布局区域的每个位置实例化。

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