公开(公告)号：US10930650B2

公开(公告)日：2021-02-23

申请号：US16450141

申请日：2019-06-24

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar Sharma

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/06

Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

公开(公告)号：US09268894B2

公开(公告)日：2016-02-23

申请号：US14279587

申请日：2014-05-16

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar Sharma ,  Manoj Sharma Kumar

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077

Abstract: A computerized method for designing a layout of a driver includes analyzing a schematic circuit. PMOSFETs coupled between first common nodes are grouped into one or more first classes. NMOSFETs coupled between second common nodes are grouped into one or more second classes. The method further includes generating the layout for each MOSFET at each location in a layout area of the driver by generating a super parameterized cell (PCELL) layout block comprising a master MOSFET PCELL and a master guard ring PCELL for each of the first class and the second class. The master MOSFET PCELL includes a first set of parameters for the MOSFET and the master guard ring PCELL includes a second set of parameters for the guard ring around the MOSFET. A child PCELL of the master MOSFET PCELL and the master guard ring PCELL are instantiated at each location in the layout area.

Abstract translation: 用于设计驱动器布局的计算机化方法包括分析原理图电路。 耦合在第一公共节点之间的PMOSFET被分组成一个或多个第一类。 耦合在第二公共节点之间的NMOSFET被分组成一个或多个第二类。 该方法还包括通过生成包括主MOSFET PCELL和主保护环PCELL的超参数化单元（PCELL）布局块来为驱动器的布局区域中的每个位置处的每个MOSFET生成布局，用于第一类和 二等。 主MOSFET PCELL包括MOSFET的第一组参数，主保护环PCELL包括围绕MOSFET的保护环的第二组参数。 主MOSFET PCELL和主保护环PCELL的子PCELL在布局区域的每个位置实例化。

公开(公告)号：US11521967B2

公开(公告)日：2022-12-06

申请号：US16908899

申请日：2020-06-23

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar Sharma

IPC: H01L27/085 ,  H01L29/739 ,  H01L29/06 ,  H01L23/482

Abstract: A substrate has an active area including first and second doped regions separated by portions of the substrate. Gates are located over the active area, each gate formed extending over a portion of the substrate separating adjacent first and second doped regions. A length of the doped regions is greater than other devices within the substrate that have a same gate oxide thickness. A first metallization layer has first electrical connectors between each of the first doped regions and a gate immediately adjacent thereto, and second electrical connectors connected to each of the second doped regions. A second metallization layer has a first electrical connector connected to each first electrical connector of the first metallization layer, and a second electrical connector connected to each second electrical connector of the first metallization layer, with the second electrical connector of the second metallization layer not overlapping the gates.

公开(公告)号：US11502078B2

公开(公告)日：2022-11-15

申请号：US17152272

申请日：2021-01-19

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar Sharma

IPC: H01L27/092 ,  H01L27/02 ,  H01L27/11 ,  H01L29/06 ,  H01L29/78 ,  H01L29/74 ,  H01L27/118

Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

公开(公告)号：US12211832B2

公开(公告)日：2025-01-28

申请号：US17504293

申请日：2021-10-18

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vishal Kumar Sharma

IPC: H01L27/02 ,  H01L29/417 ,  H01L29/739

Abstract: A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.

公开(公告)号：US11171131B2

公开(公告)日：2021-11-09

申请号：US16544206

申请日：2019-08-19

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar Sharma

IPC: H01L27/02 ,  H01L29/739 ,  H01L29/417

Abstract: A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.

公开(公告)号：US20150331985A1

公开(公告)日：2015-11-19

申请号：US14279587

申请日：2014-05-16

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar Sharma ,  Manoj Sharma Kumar

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077

Abstract: A computerized method for designing a layout of a driver includes analyzing a schematic circuit. PMOSFETs coupled between first common nodes are grouped into one or more first classes. NMOSFETs coupled between second common nodes are grouped into one or more second classes. The method further includes generating the layout for each MOSFET at each location in a layout area of the driver by generating a super parameterized cell (PCELL) layout block comprising a master MOSFET PCELL and a master guard ring PCELL for each of the first class and the second class. The master MOSFET PCELL includes a first set of parameters for the MOSFET and the master guard ring PCELL includes a second set of parameters for the guard ring around the MOSFET. A child PCELL of the master MOSFET PCELL and the master guard ring PCELL are instantiated at each location in the layout area.

Abstract translation: 用于设计驱动器布局的计算机化方法包括分析原理图电路。 耦合在第一公共节点之间的PMOSFET被分组成一个或多个第一类。 耦合在第二公共节点之间的NMOSFET被分组成一个或多个第二类。 该方法还包括通过生成包括主MOSFET PCELL和主保护环PCELL的超参数化单元（PCELL）布局块来为驱动器的布局区域中的每个位置处的每个MOSFET生成布局，用于第一类和 二等。 主MOSFET PCELL包括MOSFET的第一组参数，主保护环PCELL包括围绕MOSFET的保护环的第二组参数。 主MOSFET PCELL和主保护环PCELL的子PCELL在布局区域的每个位置实例化。