公开(公告)号：US20240332406A1

公开(公告)日：2024-10-03

申请号：US18610829

申请日：2024-03-20

Applicant: STMicroelectronics International N.V.

Inventor： Alexis GAUTHIER ,  Pascal CHEVALIER ,  Olivier WEBER ,  Franck ARNAUD

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/7394 ,  H01L29/66325

Abstract: A bipolar transistor includes a first PN junction and a second PN junction. A first gate is located on the first PN junction. A second gate is located on the second PN junction.

公开(公告)号：US20240306401A1

公开(公告)日：2024-09-12

申请号：US18587606

申请日：2024-02-26

Applicant: STMicroelectronics International N.V.

Inventor： Remy BERTHELON ,  Olivier WEBER

IPC: H10B63/00 ,  H10B63/10

CPC classification number: H10B63/32 ,  H10B63/10 ,  H10B63/80

Abstract: The present disclosure relates to a process that includes the simultaneous formation of a first transistor in and on a first region of a substrate, of a second transistor in and on a second region of the substrate, of a third transistor in and on a third region of the substrate and of a memory cell in and on a fourth region of the substrate. The method includes the following successive steps: forming a first gate stack on the first region, a second gate stack on the second region, a third gate stack on the third region and a fourth stack on line with the fourth region; simultaneously etching a part of the third gate stack and the fourth stack the first and the second gate stacks being protected with a first mask; and simultaneously etching the first and the second gate stacks, the third gate stack and the fourth region of the semiconductor substrate being protected with a second mask.