公开(公告)号：US20250027994A1

公开(公告)日：2025-01-23

申请号：US18222535

申请日：2023-07-17

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep JAIN ,  Shalini PATHAK ,  Pooja JAIN

IPC: G01R31/3185 ,  G01R31/317

Abstract: An integrated circuit improves scan testing efficiency by addressing slow Scan-OUT pins. The integrated circuit shifts data through high-frequency Scan-OUT pins every cycle and through low-frequency Scan-OUT pins every other cycle. Data that cannot be shifted through low-frequency pins is stored in an accumulator and later shifted out through high-frequency pins. Despite changing the scan-out data pattern, the tester used for testing the integrated circuit anticipates the resulting pattern, providing for the testing to not be negatively impacted.

公开(公告)号：US20240385241A1

公开(公告)日：2024-11-21

申请号：US18199065

申请日：2023-05-18

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep JAIN ,  Pooja JAIN ,  Esha PAL

IPC: G01R31/317 ,  G01R31/3183 ,  G01R31/3185

Abstract: Test circuitry includes a scan-compressor receiving n scan-input bits from n input-pins and compressing those bits for distribution among z scan-chains, z being less than n. A scan-decompressor receives test response data from the scan-chains and decompresses the test response data, reconstructing n scan-output bits. An OCC generates a test-clock based on clock-bits received from a clock-chain, with the test-clock operating the scan-chains and the clock-chain. The clock-chain receives m clock-chain input bits from m of the input-pins, m being less than n, and provides the clock-bits to the OCC for generating the test-clock. The test circuitry performs tests on the IC. Each test is associated with the test-clock generated by the OCC based on a given set of clock-bits. Tests associated with the test-clock generated by the OCC based on the same given set of clock-bits are performed after a single loading of that same given set of clock-bits.