公开(公告)号：US20250027994A1

公开(公告)日：2025-01-23

申请号：US18222535

申请日：2023-07-17

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep JAIN ,  Shalini PATHAK ,  Pooja JAIN

IPC: G01R31/3185 ,  G01R31/317

Abstract: An integrated circuit improves scan testing efficiency by addressing slow Scan-OUT pins. The integrated circuit shifts data through high-frequency Scan-OUT pins every cycle and through low-frequency Scan-OUT pins every other cycle. Data that cannot be shifted through low-frequency pins is stored in an accumulator and later shifted out through high-frequency pins. Despite changing the scan-out data pattern, the tester used for testing the integrated circuit anticipates the resulting pattern, providing for the testing to not be negatively impacted.