公开(公告)号：US20230214292A1

公开(公告)日：2023-07-06

申请号：US17567540

申请日：2022-01-03

Applicant: STMicroelectronics International N.V.

Inventor： Amulya Pandey ,  Manish Bansal ,  Sandeep Bhattacharya

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/27 ,  G06F9/30 ,  G06F9/48

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/27 ,  G06F9/30145 ,  G06F9/30101 ,  G06F9/4812

Abstract: In an embodiment, an electronic circuit includes: a plurality of signal channels; a signal collection circuit configured to determine an action of the electronic circuit based on channel signals from the plurality of signal channels; and a first signal management circuit coupled between the plurality of signal channels and the signal collection circuit, the first signal management circuit including: a set of internal registers, a set of user registers, and a decoder configured to program the set of internal registers based on a content of the set of user registers, where the first signal management circuit is configured to receive the channel signals via the plurality of signal channels, generate first aggregated signals based on the received channel signals and a content of the set of internal registers, and transmitting the first aggregated signals to the signal collection circuit.

公开(公告)号：US11698833B1

公开(公告)日：2023-07-11

申请号：US17567540

申请日：2022-01-03

Applicant: STMicroelectronics International N.V.

Inventor： Amulya Pandey ,  Manish Bansal ,  Sandeep Bhattacharya

IPC: G06F11/10 ,  G06F11/07 ,  G06F9/48 ,  G06F9/30 ,  G06F11/27

CPC classification number: G06F11/1068 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/4812 ,  G06F11/0772 ,  G06F11/27

Abstract: In an embodiment, an electronic circuit includes: a plurality of signal channels; a signal collection circuit configured to determine an action of the electronic circuit based on channel signals from the plurality of signal channels; and a first signal management circuit coupled between the plurality of signal channels and the signal collection circuit, the first signal management circuit including: a set of internal registers, a set of user registers, and a decoder configured to program the set of internal registers based on a content of the set of user registers, where the first signal management circuit is configured to receive the channel signals via the plurality of signal channels, generate first aggregated signals based on the received channel signals and a content of the set of internal registers, and transmitting the first aggregated signals to the signal collection circuit.