公开(公告)号：US20240241811A1

公开(公告)日：2024-07-18

申请号：US18155204

申请日：2023-01-17

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar GOYAL ,  Amritanshu ANAND ,  Satinder Singh MALHI

IPC: G06F11/36 ,  G06F11/07 ,  G06F11/14

CPC classification number: G06F11/3656 ,  G06F11/0772 ,  G06F11/1441

Abstract: In general, trace and debug logic should not be affected by all functional or destructive resets of a processing system. However, certain events, such as power supply related events may be utilized to reset the trace and debug logic since the trace and debug logic may cease correct operation if the provided power supply is insufficient. In addition, it may be beneficial for a debugger to initiate requests to reset trace and debug logic. Further, fault triggers from critical path monitors may be candidates as a source of reset for the trace and debug circuitry. For example, when critical path monitors trigger a fault, the fault may be from the logic associated with either trace and debug logic or the logic which is being debugged or traced. As such, in some instances both trace and debug circuitry and the processing system may be inoperable and may need to be reset.

公开(公告)号：US20150198665A1

公开(公告)日：2015-07-16

申请号：US14152879

申请日：2014-01-10

Applicant: STMicroelectronics International N.V.

Inventor： V SRINIVASAN ,  Satinder Singh MALHI ,  Tripti GUPTA

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31727 ,  G01R31/318552 ,  G01R31/318594 ,  G01R31/3187

Abstract: A system and method for testing an integrated circuit using methodologies to reduce voltage drop during ATPG and LBIST testing. In one embodiment, delay elements may be added to a clock circuit used to generate the various clock signals that trigger the switching of the various electronic components. In another embodiment, logic circuitry may be added to a clock generation circuit to isolate clock domains in order to enable a clock signal in each clock domain in a specific pattern. In yet another embodiment, capture phases for LBIST testing may be made to be asynchrounous within each capture phase, such that data capture for one LBIST partition may be timed different from other capture phases for other LBIST partitions. Finally, a further embodiment ATPG circuitry may also be partitioned such that logic circuitry only enables one (or less than all) ATPG partition at a time.

Abstract translation: 一种使用方法测试集成电路的系统和方法，以减少ATPG和LBIST测试期间的电压降。 在一个实施例中，可以将延迟元件添加到用于产生触发各种电子部件的切换的各种时钟信号的时钟电路。 在另一个实施例中，逻辑电路可以被添加到时钟发生电路以隔离时钟域，以便以特定模式启用每个时钟域中的时钟信号。 在又一个实施例中，用于LBIST测试的捕获阶段可以在每个捕获阶段内是不同步的，使得一个LBIST分区的数据捕获可以与其他LBIST分区的其他捕获阶段的时间不同。 最后，另外的实施例ATPG电路也可以被分割，使得逻辑电路一次只能启用一个（或少于所有）ATPG分区。