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公开(公告)号：US20250007497A1
公开(公告)日：2025-01-02
申请号：US18750140
申请日：2024-06-21
Applicant: STMicroelectronics International N.V.
Inventor： Stephane DUCREY , Jean Claude BINI
Abstract: An electronic circuit includes a reference clock signal generator block and functional blocks. In response to a detected failure on a signal originating from a reference frequency generator of the reference clock signal generator block, only the reference frequency generator of the reference clock signal generator block, but not the functional blocks, is reset.
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