公开(公告)号：US20200243512A1

公开(公告)日：2020-07-30

申请号：US16736949

申请日：2020-01-08

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar SHARMA ,  Varun KUMAR

IPC: H01L27/02

Abstract: A circuit includes a logic circuit and a driver. The driver includes a first NMOS having a gate coupled to the logic circuit and source coupled to a reference voltage, a PAD coupled to a drain of the first NMOS, and a driver protection circuit. The driver protection circuit includes a second NMOS having a drain coupled to the PAD through a capacitor, source coupled to the reference voltage, and gate coupled to a supply voltage, and a resistor coupled between the drain of the second NMOS and the bulk of the first NMOS. The supply voltage transitions low when an electrostatic discharge (ESD) event raises potential at the PAD with respect to either reference voltage or supply voltage such that the second NMOS turns off, resulting in isolation of the bulk of first NMOS from the reference voltage and coupling of the bulk to the PAD using the capacitor.

公开(公告)号：US20250006725A1

公开(公告)日：2025-01-02

申请号：US18744291

申请日：2024-06-14

Applicant: STMicroelectronics International N.V.

Inventor： Varun KUMAR

IPC: H01L27/02 ,  H01L21/8249

Abstract: The present disclosure is directed to an input/output (I/O) interface that includes a set of complementary metal-oxide semiconductor (CMOS) transistors in a P-type substrate. A first N-type region is in the substrate and a second N-type region in the substrate spaced from the first N-type region, the second N-type region being a deep-NWELL (DNW). A first heavily doped P-type region is between the first and second N-type regions, the first heavily doped P-type region is coupled to ground. A second heavily doped P-type region in the first N-type region, the second heavily doped P-type region and is coupled to an output terminal. A first heavily doped N-type region is in the first N-type region, the first heavily doped N-type region is coupled to a floating-Well (FW) terminal. A second heavily is doped N-type region in the second N-type region. A resistor is coupled to the DNW and the resistor is coupled to a voltage supply terminal.