公开(公告)号：US20200075575A1

公开(公告)日：2020-03-05

申请号：US16544206

申请日：2019-08-19

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar SHARMA

IPC: H01L27/02 ,  H01L29/417 ,  H01L29/739

Abstract: A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.

公开(公告)号：US20210143151A1

公开(公告)日：2021-05-13

申请号：US17152272

申请日：2021-01-19

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar SHARMA

IPC: H01L27/092 ,  H01L29/06

Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

公开(公告)号：US20220037308A1

公开(公告)日：2022-02-03

申请号：US17504293

申请日：2021-10-18

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vishal Kumar SHARMA

IPC: H01L27/02 ,  H01L29/739 ,  H01L29/417

Abstract: A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.

公开(公告)号：US20200243512A1

公开(公告)日：2020-07-30

申请号：US16736949

申请日：2020-01-08

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar SHARMA ,  Varun KUMAR

IPC: H01L27/02

Abstract: A circuit includes a logic circuit and a driver. The driver includes a first NMOS having a gate coupled to the logic circuit and source coupled to a reference voltage, a PAD coupled to a drain of the first NMOS, and a driver protection circuit. The driver protection circuit includes a second NMOS having a drain coupled to the PAD through a capacitor, source coupled to the reference voltage, and gate coupled to a supply voltage, and a resistor coupled between the drain of the second NMOS and the bulk of the first NMOS. The supply voltage transitions low when an electrostatic discharge (ESD) event raises potential at the PAD with respect to either reference voltage or supply voltage such that the second NMOS turns off, resulting in isolation of the bulk of first NMOS from the reference voltage and coupling of the bulk to the PAD using the capacitor.

公开(公告)号：US20200006339A1

公开(公告)日：2020-01-02

申请号：US16450141

申请日：2019-06-24

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar SHARMA

IPC: H01L27/092 ,  H01L29/06

Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.