公开(公告)号：US20240195432A1

公开(公告)日：2024-06-13

申请号：US18521725

申请日：2023-11-28

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Vikram SINGH

IPC: H03M3/00

CPC classification number: H03M3/458 ,  H03H21/0012

Abstract: Various examples in accordance with the present disclosure provide example methods, systems, and apparatuses that may reduce direct current (DC) bias in biased signal inputs.

公开(公告)号：US20240192314A1

公开(公告)日：2024-06-13

申请号：US18521570

申请日：2023-11-28

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Vikram SINGH

IPC: G01S7/35

CPC classification number: G01S7/35

Abstract: An apparatus, method, and system for efficiently storing proportional data is provided. An example apparatus may include a controller configured to determine a linear estimate based on input values provided to a first circuit and proportional output values received from the first circuit. The input values include a first input value proportional to a first output value and a second input value proportional to a second output value. Further, the linear estimate of the output values may be determined based on the first output value and a linear rate of change, wherein the linear rate of change corresponds to the change from the first input value to the second input value and the change from the first output value to the second output value. The apparatus may further comprise a memory, configured to store a storage value that represents an offset of an output value from the linear estimate.

公开(公告)号：US20230101518A1

公开(公告)日：2023-03-30

申请号：US18075977

申请日：2022-12-06

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Vikram SINGH

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/08

Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.

公开(公告)号：US20210409032A1

公开(公告)日：2021-12-30

申请号：US17354126

申请日：2021-06-22

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Vikram SINGH

IPC: H03M1/10

Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.