公开(公告)号：US20030056164A1

公开(公告)日：2003-03-20

申请号：US09954637

申请日：2001-09-14

Applicant: STMicroelectronics Limited

Inventor： Christophe Lauga

IPC: G01R031/28

CPC classification number: G01R31/318536 ,  G01R31/318547 ,  G01R31/318572

Abstract: A semiconductor integrated circuit, including a test scan arrangement has a plurality of scan chains arranged in pairs. These scan chains have input terminals for receiving test patterns, and outputs provided to compression logic such as a distributed XOR tree multiple input shift register to provide an output which is a compressed signal derived from the output test patterns. In an alternative configuration, the first scan chain of each pair is connected to the second scan chain of each pair, and the input terminal of the second scan chain becomes the output terminal. Thereby creating a longer scan chain of the first and second scan chains together with one input terminal and one output terminal. The two loads allow for efficient scanning in the first mode, or debugging to determine the position of a fault in the second mode.

Abstract translation: 包括测试扫描装置的半导体集成电路具有成对布置的多个扫描链。 这些扫描链具有用于接收测试图案的输入端子，以及提供给诸如分布式异或树多输入移位寄存器之类的压缩逻辑的输出，以提供作为从输出测试图案导出的压缩信号的输出。 在替代配置中，每对的第一扫描链连接到每对的第二扫描链，并且第二扫描链的输入端变为输出端。 从而创建第一和第二扫描链的更长的扫描链以及一个输入端和一个输出端。 两个负载允许在第一模式下进行有效的扫描，或者调试以确定第二模式中故障的位置。