公开(公告)号：US20040148583A1

公开(公告)日：2004-07-29

申请号：US10352799

申请日：2003-01-27

Applicant: STMicroelectronics Limited

Inventor： Andrew Hulbert ,  Enrico Gregoratto

IPC: G06F017/50

CPC classification number: G06F17/5068 ,  G06F17/505

Abstract: A method of arranging an integrated circuit to correct for hold time errors comprises fixing the position of existing cells in a design, determining hold time errors required to be corrected and placing buffer cells in spaces in the existing design. By placing buffer cells in spaces in the existing design, rather than moving cells in the existing design, the hold time can be corrected without changing the critical path.

Abstract translation: 布置集成电路以校正保持时间误差的方法包括：将设计中的现有单元的位置固定，确定需要校正的保持时间误差，并将缓冲单元放置在现有设计中的空格中。 通过将现有设计中的缓冲区放置在空格中，而不是在现有设计中移动单元格，可以在不改变关键路径的情况下更正保持时间。