公开(公告)号：US20030137861A1

公开(公告)日：2003-07-24

申请号：US10229337

申请日：2002-08-26

Applicant: STMicroelectronics Limited

Inventor： William Thies ,  Nicolas Froidevaux

IPC: G11C005/06

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/06153

Abstract: A method of producing a semiconductor circuit is disclosed with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.

Abstract translation: 公开了一种制造半导体电路的方法，与常规电路布局相比，具有节省的面积。 IO单元被布置成宽度乘以因子，但具有相应减小的高度。 与常规安排相比，ESD保护电路以降低的速度被包括在内。 通过占用由ESD电路与IO电路一起使用的半导体区域来实现节省空间。 ESD保护保持在不同的位置。