公开(公告)号：US20030158882A1

公开(公告)日：2003-08-21

申请号：US10322197

申请日：2002-12-17

Applicant: STMicroelectronics Limited

Inventor： Simon Knowles

IPC: G06F007/50

CPC classification number: G06F7/508 ,  G06F2207/5063

Abstract: A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of minimum depth. The design technique takes into account the number of logical stages of the addition circuit and the manner in which those stages are connected by spanning paths to create fan-out nodes. The number of fan-out nodes per level can be optimized. For bit lengths n, the number (mnull2) of logical stages is nnull2mnull1 and for bit lengths n not of a binary order, the number (mnull2) of logical stages is nbonull2mnull1, where nbo is the next largest binary order after n.

Abstract translation: 描述了根据该方法设计的加法电路的设计方法和加法电路。 优化设计技术，以便于设计最小深度的加法电路。 设计技术考虑了加法电路的逻辑级数和通过跨越路径连接这些级的方式来创建扇出节点。 可以优化每个级别的扇出节点数量。 对于位长度n，逻辑级数（m + 2）为n = 2m + 1，对于不是二进制顺序的位长度n，逻辑级的数量（m + 2）为nbo = 2m + 1，其中 nbo是n之后的下一个最大的二进制顺序。