公开(公告)号：US20020116426A1

公开(公告)日：2002-08-22

申请号：US10076116

申请日：2002-02-14

Applicant: STMicroelectronics Ltd.

Inventor： Parvesh Swami

IPC: G06F007/38

CPC classification number: G06F7/501 ,  G06F1/0356 ,  H03K19/17728

Abstract: A look-up table apparatus is provided for performing two-bit arithmetic operation including carry generation. The look-up table is modified to perform two concurrent combinatorial functions, or one function for an increased number of inputs. The look-up table of the present invention can implement two full adders or subtractors, or two-bit counters, for example. One portion of the modified look-up table provides two bits of a sum output, and another portion of the modified table provides a fast carry out signal for application to a next stage of an adder/subtractor/counter.

Abstract translation: 提供了一种用于执行包括进位产生的两比特算术运算的查找表装置。 查找表被修改为执行两个并发组合函数，或者一个增加数量的输入的函数。 本发明的查找表可以实现例如两个全加器或减法器或两位计数器。 经修改的查找表的一部分提供了和输出的两个比特，并且修改的表的另一部分提供了一个快速进位信号，用于应用于加法器/减法器/计数器的下一个级。