公开(公告)号：US20040052144A1

公开(公告)日：2004-03-18

申请号：US10325617

申请日：2002-12-20

Applicant: STMicroelectronics N.V. ,  STMicroelectronics SA

Inventor： Freidbert Berens ,  Michael J. Thul ,  Franck Gilbert ,  Norbert Wehn

IPC: G11C007/00

CPC classification number: H03M13/6566 ,  H03M13/2771

Abstract: In a particular embodiment using a distributed architecture, the electronic device comprises a source memory means partitioned in N elementary source memories for storing a sequence of input data, processing means clocked by a clock signal and having N outputs for producing per cycle of the clock signal N data respectively associated to N input data respectively stored in the N elementary source memories at relative source addresses, N single port target memories, N interleaving tables containing for each relative source address the number of one target memory and the corresponding relative target address therein, N cells connected in a ring structure, each cell being further connected between one output of the processing means, one interleaving table, and the port of one target memory, each cell being adapted to receive data from said output of the processing means and from its two neighbouring cells or to write at least some of these received data sequentially in the associated target memory, in accordance with the contents of said interleaving tables.

Abstract translation: 在使用分布式架构的特定实施例中，电子设备包括在N个基本源存储器中分区的源存储器装置，用于存储输入数据序列，由时钟信号计时的处理装置，并具有用于产生每个时钟信号周期的N个输出 N个数据分别与N个输入数据相关联地存储在相对源地址的N个基本源存储器中，N个单端口目标存储器，N个交织表，每个相对源地址包含一个目标存储器的数目和其中的对应的相对目标地址， N个单元以环形结构连接，每个单元进一步连接在处理装置的一个输出端，一个交织表和一个目标存储器的端口之间，每个单元适于从处理装置的输出端接收数据， 两个相邻小区或者在相关联的小区中顺序地写入这些接收的数据中的至少一些 t存储器，根据所述交织表的内容。