公开(公告)号：US20040085230A1

公开(公告)日：2004-05-06

申请号：US10615601

申请日：2003-07-07

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Abhishek Lal

IPC: H03M007/00

CPC classification number: H03M7/16

Abstract: An improved binary decoder incorporating a selection circuit that activates a selected output corresponding to a input binary value, and a deselecting circuit coupled to each output that deactivates all other outputs when the selected output is activated. The deselecting circuit arrangement has a single input connected to the selected output and a plurality of outputs each of which is connected to one of the remaining outputs and forces them to the inactive state whenever the selected output is activated.

Abstract translation: 一种改进的二进制解码器，其包括激活对应于输入二进制值的所选输出的选择电路，以及耦合到每个输出的取消选择电路，当所选择的输出被激活时，其去激活所有其它输出。 取消选择电路装置具有连接到所选择的输出的单个输入和多个输出，每个输出连接到剩余输出中的一个，并且每当选择的输出被激活时迫使它们处于非活动状态。