公开(公告)号：US20040136253A1

公开(公告)日：2004-07-15

申请号：US10679941

申请日：2003-10-06

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Anuj Gupta ,  Sanjeev Chopra

IPC: G11C007/00

CPC classification number: G11C7/065

Abstract: An improved latch-type sense amplifier circuit having two cross-coupled inverters forming a latch, a supply coupling device for selectively connecting the latch to a supply source, and a bit line coupling circuits for selectively connecting the inputs of each inverter to the complimentary bit line from the memory array. The circuit is configured to sense a voltage difference between the bit lines with improved reliability by providing a delayed sense amplifier enable signal to pass transistors for delaying disconnection of the bit lines from the sense amplifier until the latching action is completed, and adding two transistors in series with the existing transistors of the conventional latch for correcting the offset between the threshold voltages of the inverters of the latch.

Abstract translation: 具有形成锁存器的两个交叉耦合的反相器的改进的锁存型读出放大器电路，用于选择性地将锁存器连接到电源的电源耦合装置和用于选择性地将每个反相器的输入连接到补充位的位线耦合电路 线从内存阵列。 该电路被配置为通过提供延迟读出放大器使能信号来传递晶体管来延迟位线从读出放大器的断开直到闭锁动作完成，并且将两个晶体管加到 与常规锁存器的现有晶体管串联，用于校正锁存器的反相器的阈值电压之间的偏移。