公开(公告)号：US20020127850A1

公开(公告)日：2002-09-12

申请号：US10144944

申请日：2002-05-13

Applicant: STMicroelectronics S.A.

Inventor： Christophe Verove

IPC: H01L021/4763

CPC classification number: H01L21/76832 ,  H01L21/7681

Abstract: A method of manufacturing an integrated circuit is provided. According to the method, first and second stop layers are deposited on a first dielectric layer that covers a first metallization level. The second stop layer is selectively etched with respect to the first stop layer, and the first stop layer is selectively etched with respect to the first dielectric layer. A second dielectric layer and a third stop layer are deposited. The third stop layer is selectively etched with respect to the second dielectric layer, and the first and second dielectric layers are selectively etched with respect to the stop layers so as to form trenches in the second dielectric layer and holes in the first dielectric layer. Additionally, an integrated circuit is provided that includes first and second metallization levels. A dielectric layer is located between the metallization levels, and a first stop layer is located between the dielectric layer and the second metallization level. A second stop layer is located above the first stop layer, and a third stop layer is located above the dielectric material of the second metallization level. In one preferred embodiment, lines of at least one metallization levels are made of copper, and the dielectric layer is made of an organic polymer having an electrical permittivity coefficient of less than 3.