公开(公告)号：US20160005836A1

公开(公告)日：2016-01-07

申请号：US14853719

申请日：2015-09-14

Applicant: STMicroelectronics S.A.

Inventor： Pascal CHEVALIER ,  Didier CELI ,  Jean-Pierre BLANC ,  Alain CHANTRE

IPC: H01L29/66 ,  H01L27/06

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66325 ,  H01L29/737 ,  H01L29/7378

Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

Abstract translation: 本公开涉及一种方法，其包括在第一和第二隔离沟槽之间的第一区域中暴露硅衬底的表面，在第一区域中蚀刻硅衬底以在第一和第二隔离沟槽之间形成凹陷，以及形成 通过在凹部中包含SiGe的膜的选择性外延生长，异质结双极晶体管的基极。