公开(公告)号：US20040257480A1

公开(公告)日：2004-12-23

申请号：US10814621

申请日：2004-03-31

Applicant: STMicroelectronics S.A.

Inventor： Pierre Busson ,  Daniel Saias ,  Frederic Paillardet ,  Franck Montaudon

IPC: H04N005/50

CPC classification number: H04N5/4446 ,  H03D3/007 ,  H03D7/161 ,  H04L2027/0016 ,  H04L2027/0024 ,  H04N5/4401 ,  H04N5/455 ,  H04N21/426 ,  H04N21/6112

Abstract: A dual-conversion tuner firstly upconverts so as to place itself outside the receive band and then downconverts with zero intermediate frequency. A filter of the surface acoustic wave type is disposed between the two frequency transposition stages of the tuner. After baseband filtering, the signals are digitized then processed in a digital block comprising a channel decoding module. With the exception of the surface acoustic wave filter, the components are entirely embodied in integrated fashion.

Abstract translation: 首先将双转换调谐器上变频，将其自身置于接收频带外，然后以零中频下变频。 表面声波型滤波器设置在调谐器的两个频率转置级之间。 在基带滤波之后，信号被数字化，然后在包括信道解码模块的数字块中进行处理。 除了表面声波滤波器之外，组件完全以整体方式体现。

公开(公告)号：US20020003586A1

公开(公告)日：2002-01-10

申请号：US09827306

申请日：2001-04-05

Applicant: STMicroelectronics S.A.

Inventor： Pierre Busson ,  Pierre-Olivier Jouffre ,  Frederic Paillardet

IPC: H04N007/20 ,  H04N005/50

CPC classification number: H03G3/3068 ,  H03G3/3089

Abstract: A tuner includes an analog block, a digital block, and an analog/digital conversion stage connected therebetween. The analog block includes a first attenuator/controlled-gain amplifier stage connected upstream to a frequency transposition stage. The overall mean power of the entire signal received by the tuner is calculated during a phase of initialization. This overall calculated power is compared in the digital block with a first predetermined reference value corresponding to a maximum power desired at a predetermined location of the analog block. The gain of the first attenuator/amplifier stage is adjusted to minimize the deviation between the overall calculated power and the reference value. In a phase of normal operation, one of the channels of the signal received is selected, with the gain of the first attenuator/ amplifier stage being fixed.

Abstract translation: 调谐器包括模拟块，数字块和连接在它们之间的模拟/数字转换级。 模拟模块包括连接到频率转置级上游的第一衰减器/受控增益放大器级。 在初始化阶段计算由调谐器接收的整个信号的总平均功率。 该总计算功率在数字模块中与对应于模拟模块的预定位置所需的最大功率的第一预定参考值进行比较。 调整第一衰减器/放大器级的增益以最小化总计算功率与参考值之间的偏差。 在正常工作阶段，选择所接收信号的通道之一，第一衰减器/放大器级的增益是固定的。

公开(公告)号：US20020051091A1

公开(公告)日：2002-05-02

申请号：US09859731

申请日：2001-05-17

Applicant: STMicroelectronics S.A.

Inventor： Sebastien Dedieu ,  Frederic Paillardet ,  Isabelle Telliez

IPC: H04L027/20 ,  H04N005/38

CPC classification number: H03H11/22 ,  H03B27/00 ,  H03D7/125 ,  H03L7/0812 ,  H03L7/087

Abstract: At least a first base signal and a second base signal are mutually in quadrature and both are capable of mutually exhibiting a quadrature error. These signals are used to formulate two pairs of delayed signals that includes a first delayed signal that is delayed with respect to the first base signal, a second signal delayed in phase opposition with respect to the first delayed signal, a third signal delayed with respect to the second base signal, and a fourth delayed signal in phase opposition with respect to the third delayed signal. The value of each of the delays is continuously adjusted using two differential signals arising from a direct or an indirect cross-mixing of the two pairs of delayed signals to obtain the four delayed signals virtually in quadrature.

Abstract translation: 至少第一基本信号和第二基本信号相互正交，并且两者都能够相互呈现正交误差。 这些信号用于制定两对延迟信号，这两对延迟信号包括相对于第一基本信号延迟的第一延迟信号，相对于第一延迟信号相位相对延迟的第二信号，相对于第一延迟信号延迟的第三信号 第二基本信号和相对于第三延迟信号相位相反的第四延迟信号。 使用由两对延迟信号的直接或间接交叉混合产生的两个差分信号来连续地调整每个延迟的值，以获得虚拟地正交的四个延迟信号。