公开(公告)号：US20040218439A1

公开(公告)日：2004-11-04

申请号：US10766291

申请日：2004-01-26

Applicant: STMicroelectronics S.A.

Inventor： Michel Harrand ,  Joseph Bulone

IPC: G11C007/00

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C2211/4061

Abstract: The content of a few pages of the dynamic random access memory is backed up, then one tries to refresh them less quickly, for example two times less quickly, and one observes whether this does or does not cause errors. The operation is repeated on the entire memory. Depending on the number of errors that have appeared on the pages refreshed less often, the refresh period is decreased or increased. Thus, the memory self-adjusts its refresh period to what is necessary for it.

Abstract translation: 对动态随机存取存储器的几页内容进行备份，然后尝试快速刷新它们，例如快速刷新两次，一次观察是否会导致错误。 在整个存储器上重复操作。 根据刷新页面上出现的错误次数不同，刷新周期减少或增加。 因此，内存将自己的刷新周期自动调整到需要的时间。

公开(公告)号：US20020116596A1

公开(公告)日：2002-08-22

申请号：US09915761

申请日：2001-07-26

Applicant: STMicroelectronics S.A.

Inventor： Jose Sanches ,  Marco Cornero ,  Miguel Santana ,  Philippe Guillaume ,  Jean-Marc Daveau ,  Thierry Lepley ,  Pierre Paulin ,  Michel Harrand

IPC: G06F009/30 ,  G06F012/00

CPC classification number: G06F9/3814 ,  G06F9/3802 ,  G06F9/3853 ,  G06F9/3885

Abstract: A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Abstract translation: 数字信号处理器被设计为执行可包括多达N个基本指令代码的可变大小的指令。 处理器包括存储器程序，其包括I个可寻址的并行连接的存储器组，其中以隔行方式记录程序的代码，以及用于读取布置成读取每个I存储体中的代码的程序存储器的电路 在读取指令的周期中。 用于读取程序存储器中的指令的循环包括读取包括要读取的指令代码或代码的代码序列，并且还可以包括属于后续指令的代码，该代码在指令被应用于执行单元之前被过滤。 数字信号处理器的程序存储器不包括任何无操作类型的代码。